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Volumn 6, Issue 1, 2004, Pages 77-97

Efficient verification of timed automata with BDD-like data structures

Author keywords

BDD; Data structures; Model checking; Timed automata; Verification

Indexed keywords

BACKWARD REACHABILITY; BDD; CANONICAL FORM; DESIGN ISSUES; FORWARD-AND-BACKWARD; FUTURE IMPROVEMENTS; STATE SPACE REPRESENTATION; TIMED AUTOMATA;

EID: 84896693156     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s10009-003-0135-4     Document Type: Article
Times cited : (52)

References (25)
  • 3
    • 0030384792 scopus 로고    scopus 로고
    • Approximate reachability analysis of timed automata
    • December, Washington D.C., USA, IEEE Computer Society
    • Balarin F (1996) Approximate reachability analysis of timed automata. IEEE RTSS (17th IEEE Real-Time Sytems Symposium), December 1996, Washington D.C., USA, IEEE Computer Society, pp 52-61
    • (1996) IEEE RTSS (17th IEEE Real-Time Sytems Symposium , pp. 52-61
    • Balarin, F.1
  • 6
    • 84958037228 scopus 로고    scopus 로고
    • UPPAAL - a tool suite for automatic verification of real-time systems
    • Lecture notes in computer science. Springer, Berlin Heidelberg New York
    • Bengtsson J, Larsen K, Larsson F, Pettersson P, Wang Y (1996) UPPAAL - a tool suite for automatic verification of real-time systems. In: Proceedings of the hybrid control system symposium, 1996. Lecture notes in computer science. Springer, Berlin Heidelberg New York
    • (1996) Proceedings of the Hybrid Control System Symposium , pp. 1996
    • Bengtsson, J.1    Larsen, K.2    Larsson, F.3    Pettersson, P.4    Wang, Y.5
  • 8
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • Bryant RE (1986) Graph-based algorithms for Boolean function manipulation. IEEE Trans Comput C-35(8)
    • (1986) IEEE Trans Comput C-35(8)
    • Bryant, R.E.1
  • 12
    • 0031357735 scopus 로고    scopus 로고
    • Efficient verification of real-time systems: Compact data-structure and state-space reduction
    • Madrid, Spain, IEEE Computer Society, December 1998
    • Larsen KG, Larsson F, Pettersson P, Wang Y (1998) Efficient verification of real-time systems: compact data-structure and state-space reduction. IEEE RTSS (19th IEEE Real-Time Systems Symposium), Madrid, Spain, IEEE Computer Society, December 1998
    • (1998) IEEE RTSS (19th IEEE Real-Time Systems Symposium
    • Larsen, K.G.1    Larsson, F.2    Pettersson, P.3    Wang, Y.4
  • 16
    • 3042597986 scopus 로고    scopus 로고
    • Efficient data-structure for fully symbolic verification of real-time software systems
    • March 2000, Berlin. Lecture notes in computer science, Springer, Berlin Heidelberg New York
    • Wang F (2000a) Efficient data-structure for fully symbolic verification of real-time software systems. In: Proceedings of the conference on tools and algorithms for the construction and analysis of systems (TACAS 2000), March 2000, Berlin. Lecture notes in computer science, vol 1785. Springer, Berlin Heidelberg New York
    • (2000) Proceedings of the Conference On Tools and Algorithms For the Construction and Analysis of Systems (TACAS 2000 , vol.1785
    • Wang, F.1
  • 17
    • 0034513970 scopus 로고    scopus 로고
    • Region encoding diagram for fully symbolic verification of real-time systems
    • October 2000, Taipei, Taiwan, ROC. IEEE Computer Society, IEEE Press, New York
    • Wang F (2000b) Region encoding diagram for fully symbolic verification of real-time systems. In: Proceedings of the the 24th COMPSAC (24th Computer Software and Applications Conference), October 2000, Taipei, Taiwan, ROC. IEEE Computer Society, IEEE Press, New York, pp 509-515
    • (2000) Proceedings of the The 24th COMPSAC (24th Computer Software and Applications Conference , pp. 509-515
    • Wang, F.1
  • 18
    • 35048819139 scopus 로고    scopus 로고
    • RED: Model-checker for timed automata with clock-restriction diagram
    • ISSN 1404-3203, Department of Information Technology, Uppsala University, Uppsala, Sweden
    • Wang F (2001a) RED: Model-checker for timed automata with clock-restriction diagram. In: Proceedings of the workshop on real-time tools, August 2001. Technical Report 2001-014, ISSN 1404-3203, Department of Information Technology, Uppsala University, Uppsala, Sweden
    • (2001) Proceedings of the Workshop On Real-time Tools, August 2001. Technical Report 2001-014
    • Wang, F.1
  • 23
    • 35248871701 scopus 로고    scopus 로고
    • TCTL inevitability analysis of dense-time systems
    • July 2003, Santa Barbara, CA. Lecture notes in computer science, Springer, Berlin Heidelberg New York
    • Wang F, Hwang G-D, Yu F (2003a) TCTL inevitability analysis of dense-time systems. In: Proceedings of the 8th conference on implementation and application of automata (CIAA), July 2003, Santa Barbara, CA. Lecture notes in computer science, vol 2759. Springer, Berlin Heidelberg New York
    • (2003) Proceedings of the 8th Conference On Implementation and Application of Automata (CIAA , vol.2759
    • Wang, F.1    Hwang, G.-D.2    Yu, F.3
  • 25
    • 84896693998 scopus 로고    scopus 로고
    • Kronos: A verification tool for real-time systems
    • Yovine S (1997) Kronos: a verification tool for real-time systems. Int J Softw Tools Technol Transfer 1(1/2)
    • (1997) Int J Softw Tools Technol Transfer , vol.1 , Issue.1-2
    • Yovine, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.