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Volumn 4, Issue 1, 2002, Pages 125-137

Program slicing for VHDL

Author keywords

Formal verification; Hardware description languages; Model checking; Program slicing; VHDL

Indexed keywords

EXECUTION SEMANTICS; FORMAL VERIFICATIONS; INTER-PROCEDURAL; PROGRAM SLICING; REDUCTION TECHNIQUES; SEQUENTIAL LANGUAGES; STATIC PROGRAM ANALYSIS; VHDL;

EID: 84896693056     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s100090100069     Document Type: Article
Times cited : (14)

References (28)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.