Model checking VHDL with CV

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1522, Issue , 1998, Pages 508-514

  Deharbe, David ^a   Shankar, Subash ^b   Clarke, Edmund M ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO NORTE   (Brazil)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS;

COMPLEX CIRCUITS; CONTROL LOGIC; MODEL CHECKER; PROTOTYPE IMPLEMENTATIONS; REAL CIRCUITS; RISC MICROPROCESSORS; SEARCH SPACES; SYMBOLIC MODEL CHECKERS;

MODEL CHECKING;

EID: 26544435053     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49519-3_33     Document Type: Conference Paper

References (7)

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2. R.E. Bryant. Graph-based algorithm for boolean function manipulation. IEEE Transactions on Computers, C(35):1035-1044, 1986.
3. E.M. Clarke, E.A. Emerson, and A.P. Sistla. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems, 8(2):244-263, April 1986.
4. O. Coudert and J.-C. Madre. Symbolic computation of the valid states of a sequential machine: algorithms and discussion. In International workshop on formal methods for correct VLSI design, Miami, January 1991. ACM/IFIP WG10.2.
5. D. Deharbe and D. Borrione. Semantics of a verification-oriented subset of VHDL. In P.E. Camurati and H. Eveking, editors, CHARME’95: Correct Hardware Design and, Verification Methods, volume 987 of Lecture Notes in Computer Science, Frankfurt, Germany, October 1995. Springer Verlag.
6. IEEE. IEEE Standard VHDL Language Reference Manual, 1987. Std 1076-1987.
7. C. Delgado Kloos and P. Breuer, editors. Formal Semantics for VHDL, volume 307 of Series in Engineering and Computer Science. Kluwer Academic Publishers, 1995.