Partial set for flip-flops based on state requirement for non-scan BIST scheme

Proceedings - European Test Workshop 1999, ETW 1999

Volumn , Issue , 1999, Pages 104-109

  Flottes, M L ^a   Landrault, C ^a   Petitqueux, A ^a  

^a LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; TESTING;

CIRCUIT UNDER TEST; FAULT COVERAGES; ON STATE; PARTIAL RESETS; PSEUDO RANDOM; TEST SEQUENCE; TESTABILITY;

FLIP FLOP CIRCUITS;

EID: 84895168013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.1999.804306     Document Type: Conference Paper

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