High-speed single-electron memory: Cell design and architecture

Proceedings - 2nd International Workshop on Physics and Modeling of Devices Based on Low-Dimensional Structures

Volumn 1998-March, Issue , 1998, Pages 67-72

  Mizuta, Hiroshi ^a   Williams, David ^a   Katayama, Kozo ^a   Müller, Heinz Olaf ^a   Nakazato, Kazuo ^a   Ahmed, Haroon ^b  

^a HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MONTE CARLO METHODS; RANDOM ACCESS STORAGE;

CELL DESIGN; HIGH SPEED RAM; NOVEL ARCHITECTURE; OPERATION SCHEMES; SILICON-BASED; SINGLE ELECTRON MEMORY; SINGLE ELECTRON SIMULATION; WRITE OPERATIONS;

MEMORY ARCHITECTURE;

EID: 84893813923     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LDS.1998.714536     Document Type: Conference Paper

References (6)

1. [l] K. N-to, R. Blaikie and H. Ahmed. "Singleelectron memory", J. Appl. Phys. 75, 5123, 1994.
2. J. J. Welser, S. Tiwari, S. Rishton, K. K. Lee, aml Y. Lee, "Room tempetature operation of a quantum+k% flash memory, ED43, 1553, 1996, also in Appl. Phys. L..ett. 68, 1377 1996.
3. L. Gue, E. Leobandung and S. Chou, "A roomhemperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ulaanafro w channel". Appl. Phys. Len. 70, 850. 1997.
4. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi. F. Murai, and K. Seki. "Room-temperature single-electron memory", IEEE Trans. on Electron Devices, ED41. 1628, 1994.
5. K. Nakazato and J. White, "Single-electron switch for phase-locked single-electron logic devtces". Prm of IEDM 92. 487, 1992.
6. N. Korotkov and K. K. Likharev, -Analysis of Q, - mdependent Single-Electron Systems Inr. W&hop on Computational Electronics (IWCE). Tempe. Arizona, 1995.