Data cache sizing for embedded processor applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 925-926

  Panda, Preeti Ranjan ^a   Dutt, Nikil D ^a   Nicolau, Alexandru ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS PATTERNS; ANALYTICAL PREDICTIONS; ASSIGNMENT STRATEGIES; DATA CACHES; EMBEDDED PROCESSORS; HARDWARE RESOURCES; LINE ASSIGNMENTS; SILICON AREA;

CACHE MEMORY;

EID: 84893803526     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655972     Document Type: Conference Paper

References (3)

1. P. R. Panda, N. Dutt, and A. Nicolau "Data Cache Sizing for Embedded Processor Applications," TR-ICS-97-31, U. C. Irvine, 1997.
2. P. R. Panda, N. Dutt, and A. Nicolau "Architectural Exploration and Optimization of Local Memory in Embedded Systems", 10th International Symposium on System Synthesis, September 1997.
3. P. R. Panda, N. Dutt, and A. Nicolau "Memory Data Organization for Improved Cache Performance in Embedded Processor Applications," ACM TODAES, Vol. 2, No. 4, October 1997.