Development of a tool-set for remote and partial reconfiguration of FPGAs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 1122-1123

  Gehm Moraes, Fernando ^a   Mesquita, Daniel ^a   Carlos Palma, José ^a   Moller, Leandro ^a   Calazans, Ney ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING PRINCIPLES; FPGA DEVICES; INTERNAL ARCHITECTURE; PARTIAL RECONFIGURATION; RECONFIGURABLE SYSTEMS;

DIGITAL DEVICES; EXHIBITIONS; STRUCTURAL DESIGN; TOOLS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84893791879     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253763     Document Type: Conference Paper

References (5)

1. ATMEL. Field Programmable System Level Integrated Circuits (FPSLIC) (Aug. 2002). http://www.atmel.com/atmel/products/prod39.htm
2. XILINX. Virtex series configuration architecture user guide. Application Note nb. 151, http://www.xilinx.com/ xapp/xapp151.pdf (Mar. 2000
3. Hartenstein, R. A decade of reconfigurable computing: A visionary retrospective . In: Design, Automation and Test in Europe, pp. 642-649, 2001
4. Dyer, M.; Plessl, C.; Platzner Marco. Partially Reconfigurable Cores for Xilinx Virtex. In: Field Programmable Logic and Applications (FPL?2002), 2002
5. XILINX. Two Flows for Partial Reconfiguration: Core Based or Small Bit Manipulations. Application Note nb. 290. http://www.xilinx.com/xapp/xapp290.pdf (May 2002