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Volumn , Issue , 2000, Pages 419-422

A novel high speed low power logic family: Race logic

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN LOGIC OPERATIONS; CARRY LOOK-AHEAD ADDER; DELAY TIME; HIGH SPEED; HIGH-SPEED LOW-POWER; LOGIC FAMILIES; LOGIC STYLE; LOW POWER APPLICATION;

EID: 84893791590     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (9)
  • 1
    • 0021411604 scopus 로고
    • Dynamic logic cmos circuits
    • April
    • V. Friedman and S. Liu, "Dynamic Logic CMOS Circuits," IEEE Journal of Solid-State Circuits, Vol. SC-19. No. 2, April 1984, pp. 263-266.
    • (1984) IEEE Journal of Solid-State Circuits , vol.SC-19 , Issue.2 , pp. 263-266
    • Friedman, V.1    Liu, S.2
  • 2
    • 0031119401 scopus 로고    scopus 로고
    • Design and implementatino of differential cascode voltage switch with pass-gate (dcvspg) logic for high performance digital systems
    • April
    • Fang-shi Lai and Wei Hwang, "Design and Implementatino of Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) Logic for High performance Digital Systems," IEEE Journal of Solid-State Circuits, Vol.32, No. 4, April 1997, pp. 563-573
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , Issue.4 , pp. 563-573
    • Lai, F.-S.1    Hwang, W.2
  • 3
    • 0008690193 scopus 로고    scopus 로고
    • A 150mhz 8-banks 256m synchronous dram with wave pipelining methods
    • Hoi-Jun Yoo, etal., "A 150MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methods" International Solid-State Circuit Conference, Vol 38, pp. 250-253.
    • International Solid-State Circuit Conference , vol.38 , pp. 250-253
    • Yoo, H.-J.1
  • 5
    • 0025419522 scopus 로고
    • A 3.8ns cmos 16 x 16 multiplier using complementary pass transistor logic
    • April
    • K.Yano, etal., "A 3.8ns CMOS 16 x 16 multiplier using complementary pass transistor logic," IEEEE Journal of Solid-State Circuits, Vol.25, No. 2, April, 1990, pp. 388-395
    • (1990) IEEEE Journal of Solid-State Circuits , vol.25 , Issue.2 , pp. 388-395
    • Yano, K.1
  • 6
    • 0022701054 scopus 로고
    • Sample-set differential logic (ssdl) for complex high-speed vlsi
    • April
    • T.A. Grotjohn, etal. "Sample-Set Differential Logic (SSDL) for Complex High-Speed VLSI", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 2, April, 1986 pp. 367-369
    • (1986) IEEE Journal of Solid-State Circuits , vol.SC-21 , Issue.2 , pp. 367-369
    • Grotjohn, T.A.1
  • 7
    • 4043057560 scopus 로고    scopus 로고
    • Design methodology for high speed and low power digital circuits with energy economized pass-transistor logic (eepl
    • Neuchatel, Switzerland, Sept.
    • M. Song, etal., "Design Methodology for High Speed and Low Power Digital Circuits with Energy Economized Pass-transistor Logic (EEPL)," Proceedings of 22nd European Solid-State Circuits Conference, Neuchatel, Switzerland, Sept. 1996, pp. 120-123.
    • (1996) Proceedings of 22nd European Solid-State Circuits Conference , pp. 120-123
    • Song, M.1
  • 8
    • 0027694895 scopus 로고
    • A 1.5ns 32b cmos alu in double pass-transistor logic
    • November
    • M. Suzuki, etal., "A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic," IEEE Journal of Solid-State Circuits, Vol.28, No. 11, November 1993. pp.1145-1151
    • (1993) IEEE Journal of Solid-State Circuits , vol.28 , Issue.11 , pp. 1145-1151
    • Suzuki, M.1
  • 9
    • 0031379067 scopus 로고    scopus 로고
    • Differential and pass-transistor cmos logic for high performance systems
    • Nis, Yugoslavia, Sept.
    • V. Oklobdzija, etal., "Differential and Pass-Transistor CMOS Logic for High Performance Systems," Proceedings of the 21st International Conference on Microelectronices, Vol2, Nis, Yugoslavia, Sept. 1997, pp. 803-810.
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    • Oklobdzija, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.