A model for system-level timed analysis and profiling

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 204-210

  Allara, A ^a   Fornaciari, W ^b,c   Salice, F ^c   Sciuto, D ^b  

^a Italtel SpA   (Italy)

^b POLITECNICO DI MILANO   (Italy)

^c CEFRIEL   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAD SIMULATIONS; DESIGN ALTERNATIVES; EMBEDDED APPLICATION; MODELING STRATEGY; PROFILING INFORMATIONS; SIMULATION ALGORITHMS; SYSTEM MODULES; TIMING PROPERTIES;

PRODUCT DESIGN;

DIGITAL STORAGE;

EID: 84893775113     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655858     Document Type: Conference Paper

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