A co-synthesis approach to embedded system design automation

Design Automation for Embedded Systems

Volumn 1, Issue 1-2, 1996, Pages 69-120

  Gupta, Rajesh K ^a   De Micheli, Giovanni ^b  

^a Digital Computer Laboratory   (United States)

^b Stanford University   (United States)

Author keywords

Constraint analysis; Embedded system co synthesis; Multithreading for embedded systems

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTER HARDWARE; COMPUTER SOFTWARE; CONSTRAINT THEORY; MICROCOMPUTERS; PROBABILITY; SYSTEMS ANALYSIS;

CONSTRAINT SATISFIABILITY ANALYSIS; EMBEDDED SYSTEM DESIGN AUTOMATION; MULTITHREADING FOR EMBEDDED SYSTEM; OPERATION LEVEL TIMING CONSTRAINTS; PRE DESIGNED REPROGRAMMABLE COMPONENTS;

COMPUTER AIDED DESIGN;

EID: 0029779451     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1007/bf00134684     Document Type: Article

References (47)

1. th Annual Computer Industry Almanac 1993. The Reference Press, Austin, TX, 1993.
2. M. L. Bader, "Market survey," Bader Associates, Mountain View, California, 1993.
3. J. Aylor, R. Camposano, M. Schuette, W. Wolf, and N. Woo, "The future of embedded system design," in Proc. International Conference on Computer Design, pp. 144-146, 1992.
4. W. Wolf, "Hardware-Software Co-design of Embedded Systems," IEEE Proceedings, vol. 82, no. 7, pp. 965-989, July 1994.
5. D. D. Gajski, F. Vahid, S. Narayan, and J. Gong, Specification and Design of Embedded Systems. Prentice Hall, 1994.
6. M. Chiodo, P. Giusto, , A. Jurecska, A. Jurecska, A. S. Vincentelli, and L. Lavagno, "Hardware-software codesign of embedded systems," IEEE Micro, vol. 14, no. 4, pp. 26-36, Aug. 1994.
7. D. E. Thomas, J. K. Adams, and H. Schmit, "A Model and Methodology for Hardware-Software Codesign," IEEE Design & Test of Computers, pp. 6-15, Sept. 1993.
8. A. Kalavade and E. A. Lee, "A Hardware-Software Codesign Methodology for DSP Applications," IEEE Design and Test Magazine, pp. 16-28, Sept. 1993.
9. D. Harel, "Biting the silver bullet," IEEE Computer, pp. 8-20, Jan. 1992.
10. N. Halbwachs, Synchronous programming of reactive systems. Kluwer Academic, 1993.
11. A. Burns and A. Wellings, Real-Time Systems and Their Programming Languages. Addison-Wesley, 1990.
12. D. Ku and G. D. Micheli, High-level Synthesis of ASICs under Timing and and Synchronization Constraints. Kluwer Academic Publishers, 1992.
13. V. Cerf, Multiprocessors, Semaphores and a Graph Model of Computation. PhD thesis, UCLA, Apr. 1972.
14. D. Bustard, J. Elder, and J. Welsh, Concurrent Program Structures, Prentice Hall, 1988.
15. B. Dasarathy, "Timing Constraints of Real-Time Systems: Constructs for Expressing Them, Method of Validating Them," IEEE Trans. Software Engineering, vol. SE-11, no. 1, pp. 80-86, Jan. 1985.
16. J. F. Allen, "Maintaining knowledge about temporal intervals," Communications ACM, vol. 26, no. 11, pp. 832-843, Nov. 1983.
17. D. Ku and G. D. Micheli, "Relative Scheduling Under Timing Constraints: Algorithms for High-Level Synthesis of Digital Circuits," IEEE Transactions on CAD/ICAS, vol. 11, no. 6, pp. 696-718, June 1992.
18. R. K. Gupta, Co-Synthesis of Hardware and Software for Digital Embedded Systems. Kluwer Academic Publishers, Boston, 1995.
19. th Design Automation Conference, pp. 690-693, June 1991.
20. T. Kolks, B. Lin, and H. D. Man, "Sizing and Verification of Communication Buffers for Communicating Processes," in Proc. IEEE International Conference on Computer-Aided Design, pp. 660-664, Nov. 1993.
21. A. Mathur and R. K. Gupta, "Rate analysis for embedded systems," technical report, Computer Science, University of Illinois, 1995.
22. D. R. Cox and W. L. Smith, Queues.John Wuey and Sons, 1961.
23. A. Heck, Introduction to Maple. Springer-Verlag, 1993.
24. A. Mok, Fundamental Design Problems of Distributed Systems for the Hard-Real-Time Environment. PhD thesis, M.I.T., 1983.
25. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. W. H. Freeman and Company, 1979.
26. A. V. Aho, R. Sethi, and J. D. Ullman, Compilers: Principles, Techniques and Tools. Addison Wesley, 1986.
27. A. Shaw, "Reasoning about Time in Higher Level Language Software," IEEE Trans. Software Engg., vol. 15, no. 7, pp. 875-889, July 1989.
28. A. Mok and et. al., "Evaluating Tight Execution Time Bounds of Programs by Annotations," in Proc. IEEE Workshop Real-Time Operating Systems and Software, pp. 74-80, May 1989.
29. th IEEE Real-Time Systems Symposium, pp. 72-81, Dec. 1990.
30. W. Hardt and R. Camposano, "Trade-offfs in HW/SW Codesign," in International Workshop on Hardware-Software Co-design, Oct. 1993.
31. C. Y. Park, "Predicting program execution times by analyzing static and dynamic program paths," Real-Time Systems, vol. 5, no. 1, pp. 31-62, Mar. 1993.
32. W. Ye, R. Ernst, T. Benner, and J. Henkel, "Fast timing analysis for hardware-software co-synthesis," in Proc. International Conference on Computer Design, 1993.
33. P. Chou and G. Borriello, "Software scheduling in the Co-Synthesis of Reactive Real-Time Systems," in Proc. Design Automation Conference, June 1994.
34. R. K. Gupta and G. D. Micheli, "Constrained software generation for hardware-software systems," in Proc. Third Intl. Workshop on Hardware-Software Co-design, Sept. 1994.
35. S. Kumar, J. H. Aylor, B. W. Johnson, and W. A. Wulf, "A Framework for Hardware/Software Codesign," Computer, vol. 25, no. 12, pp. 39-45, Dec. 1993.
36. J. G. D'Ambrosio and X. Hu, "Configuration-level hardware/software partitioning for real-time embedded systems," in Proc. Intl. Workshop on Hardware/Software Codesign, 1994.
37. F. Vahid and D. D. Gajski, "Specification partitioning for system design," in Proc. Design Automation Conference, 1992.
38. E. Barros, W. Rosenstiel, and X. Xiong, "Hardware/Software Partitioning with UNITY," in Workshop on Hardware/Software Co-design, Oct. 1993.
39. G. Menez, M. Auguin, F. Boeri, and C. Carriere, "A Partitioning Algorithm for System-Level Synthesis," in Proc. IEEE International Conference on Computer-Aided Design, pp. 482-487, Nov. 1992.
40. R. Ernst, J. Henkel, and T. Benner, "Hardware-Software Cosynthesis for Microcontrollers," IEEE Design & Test of Computers, pp. 64-75, Dec. 1993.
41. T. B. Ismail, K. O'Brien, and A. Jerraya, "Interactive system-level partitioning with PARTIF," in Proc. European Design Automation Conference, 1994.
42. R. K. Gupta and G. D. Micheli, "Vulcan - A System for High-Level Partitioning of Synchronous Digital Systems," CSL Technical Report CSL-TR-471, Stanford University, Apr. 1991.
43. B. W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell System Technical Journal, vol. 49, pp. 291-307, Feb. 1970.
44. V. Sarkar, Partitioning and scheduling parallel programs for multiprocessors. MIT Press, Cambridge, Mass., 1989.
45. G. D. Micheli, D. C. Ku, F. Mailhot, and T. Truong, "The Olympus Synthesis System for Digital Design," IEEE Design and Test Magazine, pp. 37-53, Oct. 1990.
46. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach.Morgan-Kaufman, 1990.
47. R. Gupta and G. D. Micheli, "Partitioning of Functional Models of Synchronous Digital Systems," in Proc. IEEE International Conference on Computer-Aided Design, pp. 216-219, Nov. 1990.