A low-power SRAM with resonantly powered data, address, word, and bit lines

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 364-367

  Tzartzanis, Nestoras ^a   Athas, William ^b   Svensson, Lars ^c  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b HOUSE EAR INSTITUTE   (United States)

^c SwitchCore AB   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CLOCK VOLTAGE; CORE SIZE; LOW-POWER SRAM; PROTOTYPE CHIP; RESONANT DRIVER; SUPPLY VOLTAGES;

CLOCKS;

MICROPROCESSOR CHIPS;

EID: 84893755154     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. J. Montanaro, et al., A 160-MHz, 32-b, 0.5-W, CMOS RISC Microprocessor, IEEE JSSC, vol. 31, no. 11, Nov. 1996.
2. B. Amrutur, M. Horowitz, A Replica Technique for Wordline and Sense Control in Low-Power SRAM's, IEEE JSSC, vol. 33, no. 8, Aug. 1998.
3. J. Alowersson, P. Andersson, SRAM Cells for Low-Power Write in Buffer Memories, 1995 Symposium on Low Power Electronics, San Jose, CA, Oct. 9-11, 1995.
4. M. Matsumiya, et al., A 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture, IEEE JSSC, vol. 27, no. 11, Nov. 1992.
5. W. Athas, Energy-Recovery CMOS, in Low Power Design Methodologies, edited by J. Rabaey, M. Pedram, Kluwer Academic Publishers, 1996.
6. W. Athas, N. Tzartzanis, L. Svensson, L. Peterson, A Low-Power Microprocessor Based on Resonant Energy, IEEE JSSC, vol. 32, no. 11, Nov. 1997.
7. W. Athas, et. al., Clock-Powered CMOS VLSI Graphics Processor for Embedded Display Controller Application, ISSCC Digest of Technical Papers, Feb. 7-9, 2000.
8. W. Athas, L. Svensson, N. Tzartzanis, A Resonant Signal Driver For Two-Phase, Almost-Non-Overlapping Clocks, Proc. of the ISCAS 1996, Atlanta, GA, May 12-15, 1996.
9. L. Glasser, D. Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley, Reading, MA, 1985.
10. E. Seevinck, P. van Beers, H. Ontrop, Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's, IEEE JSSC, vol. 26, no. 4, Apr. 1991.
11. T. Blalock, R. Jaeger, A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier, IEEE JSSC, vol. 26, no. 4, Apr. 1991.