Control circuit templates for asynchronous bundled-data pipelines

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 1098-

  Tugsiriavisut, Sunan ^a   Beerel, Peter A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CONTROL CIRCUITS; BUNDLED DATA; CONTROL CIRCUIT TEMPLATES; CONTROL OVERHEAD; DATA-PATHS; LOW POWER; PIPELINE STAGES;

ASYNCHRONOUS SEQUENTIAL LOGIC; EXHIBITIONS; LOW POWER ELECTRONICS;

PIPELINES;

EID: 84893729066     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998454     Document Type: Conference Paper

References (3)

1. A. Lines, Pipeline Asynchronous Circuits, M.S. thesis, California Institute of Technology, 1998.
2. C. H. van Berkel, M. B. Josephs, and S. M. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223-233, Feb. 1999.
3. S. Tugsinavisut and P.A. Beerel, Control circuit templates for asynchronous bundled-data pipelines. Technical Report CENG 01-06, EE-Systems, USC, December 2001.