A 3.2-mA 6-bit pipelined A/D converter for a bluetoothTM1RF transceiver

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 547-550

  Kudoh, Junya ^a   Matsuura, T ^a   Imaizumi, E ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMMON MODE FEEDBACK; EFFECTIVE NUMBER OF BITS; LOW-POWER CONSUMPTION; OFFSET COMPENSATION; PIPELINE ARCHITECTURE; PIPELINED A/D CONVERTERS; PIPELINED ANALOG-TO-DIGITAL CONVERTER; SWITCHED CAPACITOR;

ANALOG TO DIGITAL CONVERSION; BICMOS TECHNOLOGY; BLUETOOTH; SPACE OPTICS;

MICROPROCESSOR CHIPS;

EID: 84893706401     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Specification of the Bluetooth System Version 1.0B, December 1999.
2. M. Yotsuyanagi et al., "A 1.5V, 8mW, 8b, 15Msps BiCMOS A/D Converter" Analog Integrated Circuit and Signal Processing 25, pp. 227-234, 2000
3. T. Matsuura et al., "A240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter" IEEE Journal of Solid-State Circuit., Vol 33, NO.11 November, 1998.
4. D.A. Johns, K. Martin, "Analog Integrated Circuit Design" John Wiley & Sons, Inc. 1997, p. 278 and p. 291