Potentials of chip-package co-design for high-speed digital applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 423-424

  Troster, Gerhard ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP PACKAGE CODESIGN; DIGITAL APPLICATIONS; ELECTRONIC DESIGN; HIGH-DENSITY PACKAGING; PACKAGING LEVELS; SI TECHNOLOGY; SYSTEM ARCHITECTURES; SYSTEM FUNCTIONALITY;

CHIP SCALE PACKAGES; EXHIBITIONS;

DESIGN;

EID: 84893609317     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761159     Document Type: Conference Paper

References (11)

1. The National Technology Roadmap for Semiconductors, Semiconducors Industry Association, San Jose (1997).
2. Q. Zhu,S. Tam, "Package Clock Distribution Design Optimization for High-Speed and Low-Power VLSI's," IEEE Trans. Comp. Pack. Manuf. Technology, vol 20, Feb. 1997, pp.56-63.
3. D. Patterson et al, " A Case for Intelligent RAM," IEEE Micro, March/April 1997, pp. 34-44.
4. E. Hirt, M. Scheffler, J.-P. Wyss, "Area I/O's Potentials for Future Processor Systems," IEEE Micro, 1998 July/August, pp. 42-49.
5. A.G. George, P. Krusius, R. Granitz, "Packaging Alternatives to Lrge Silicon Chips: Tiled Silicon on MCM and PWB Substrates," IEEE Trans.Comp.Pack.Manufact. Technology, vol 19, Nov. 19996, pp. 699-708.
6. L.Schaper et al, "Seamless High Off-Chip Connectivity (SHOCC)," Proc. of the International Workshop on Chip-Package Co-Design, 1998 Zürich, pp. 39-45.
7. V.Garg et al, "Early Analysis of Cost/Performance Trade-Offs in MCM Systems," IEEE Trans. Comp. Pack. Manufact. Technology, vol.20, August 1997, pp.308-319.
8. M.Scheffler et al, "Modeling and Optimization the Costs of Electronic Systems," IEEE Design&Test, July-September 1998, pp.20-26.
9. IPDI-98: IEEE Symposium on IC/Package Design Integration. http://www.cse.ucsc.edu/-lisa/ipdi
10. CPD'98: International Workshop on Chip-Package Codesign. http.//www.ife.ethz.ch/CPD98
11. IEEE Micro, vol. 18, No 4, July/August 1998, Special Issue on Chip-Package Co-design