A prototype hybrid pixel detector ASIC for the CLIC experiment

Journal of Instrumentation

Volumn 9, Issue 1, 2014, Pages

  Valerio, P ^a   Alozy, J ^a   Arfaoui, S ^a   Ballabriga, R ^a   Benoit, M ^a   Bonacini, S ^a   Campbell, M ^a   Dannheim, D ^a   De Gaspari, M ^a   Felici, D ^a   Kulis, S ^a   Llopart, X ^a   Nascetti, A ^b   Poikela, T ^a,c   Wong, W S ^a  

^a CERN   (Switzerland)

^b SAPIENZA UNIVERSITY OF ROME   (Italy)

^c TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

Author keywords

Analogue electronic circuits; Data acquisition circuits; Digital electronic circuits; Front end electronics for detector readout

Indexed keywords

65 NM CMOS TECHNOLOGIES; ANALOGUE ELECTRONICS; DATA ACQUISITION CIRCUIT; DETECTOR READOUT; DIGITAL ELECTRONIC CIRCUITS; ELECTRICAL MEASUREMENT; HYBRID PIXEL DETECTORS; TIME OVER THRESHOLDS;

CMOS INTEGRATED CIRCUITS; DATA COMPRESSION;

READOUT SYSTEMS;

EID: 84893120369     PISSN: None     EISSN: 17480221     Source Type: Journal    
DOI: 10.1088/1748-0221/9/01/C01012     Document Type: Article

References (4)

1. M. Aicheler et al., A Multi-TeV linear collider based on CLIC technology: CLIC Conceptual Design Report, CERN-2012-007.
2. L. Linssen, A. Miyamoto, M. Stanitzki, H. Weerts, Pysics and Detectors at CLIC: CLIC Conceptual Design Report, CERN-2012-003.
3. S. Bonacini et al., Characterization of a commercial 65 nm CMOS technology for SLHC applications, 2012 JINST 7 P01015.
4. F. Krummenacher, Pixel detectors with local intelligence: an IC designer point of view, Nucl. Instrum. Meth. A 305 (1991) 527.