Characterization of a commercial 65 nm CMOS technology for SLHC applications

Journal of Instrumentation

Volumn 7, Issue 1, 2012, Pages

  Bonacini, S ^a   Valerio, P ^a,b   Avramidou, R ^c   Ballabriga, R ^a   Faccio, F ^a   Kloukinas, K ^a   Marchioro, A ^a  

^a CERN   (Switzerland)

^b SAPIENZA UNIVERSITY OF ROME   (Italy)

^c NATIONAL TECHNICAL UNIVERSITY OF ATHENS   (Greece)

Author keywords

Digital electronic circuits; Front end electronics for detector readout; Radiation damage to electronic components; Radiation hard electronics

Indexed keywords

EID: 84856940918     PISSN: None     EISSN: 17480221     Source Type: Journal    
DOI: 10.1088/1748-0221/7/01/P01015     Document Type: Article

References (6)

1. L. Gonella et al. 2007 Total ionizing dose effects in 130 nm commercial CMOS technologies for HEP experiments, Nucl. Instrum. Meth. A 582 750
2. F. Faccio and G. Cervelli 2005 Radiation-induced edge effects in deep submicron CMOS transistors, \emph{{IEEE Trans. Nucl. Sci.} 52 2413}
3. M. Huhtinen and F. Faccio 2000 Computational method to estimate single event upset rates in an accelerator environment, Nucl. Instrum. Meth. A 450 155
4. L. Pierobon, S. Bonacini, F. Faccio and A. Marchioro Single-event upset sensitivity of latches in a 90nm dual and triple well CMOS technology, in Topical Workshop on Electronics for Particle Physics, Vienna, Austria, TU Wien, September 2011
5. S. Bonacini, K. Kloukinas and A. Marchioro 2007 Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components, JINST 2 P09009
6. S. Bonacini 2010 Design and characterization of an SEU-robust register in 130 nm CMOS for application in HEP ASICs, JINST 5 C11019