Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 165-167

  Park, K C ^a   Kim, I R ^a   Suh, B S ^a   Choi, S M ^a   Song, W S ^a   Wee, Y J ^a   Lee, S G ^a   Chung, J S ^a   Chung, J H ^a   Hah, S R ^a   Ahn, J H ^a   Lee, K T ^a   Kang, H K ^a   Suh, K P ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Annealing; Chemical vapor deposition; Contact resistance; Dielectrics; Electrical resistance measurement; Glass; Large scale integration; Testing; Thermal resistance; Thermal stability

Indexed keywords

ANNEALING; CHEMICAL STABILITY; CHEMICAL VAPOR DEPOSITION; CONTACT RESISTANCE; DEPOSITION; DIELECTRIC MATERIALS; GLASS; HEAT RESISTANCE; INTEGRATION TESTING; LSI CIRCUITS; METALS; PHYSICAL VAPOR DEPOSITION; TESTING; THERMODYNAMIC STABILITY; VAPOR DEPOSITION;

BARRIER METAL DEPOSITION; CONFORMAL DEPOSITION; CU-INTERCONNECTS; ELECTRICAL RESISTANCE MEASUREMENT; INTER-METAL DIELECTRICS; IONIZED PHYSICAL VAPOR DEPOSITION; PVD-BARRIER METAL; VIA RESISTANCE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84892293795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219743     Document Type: Conference Paper

References (3)

1. K. Ueno, M. Suzuki, A. Matsumoto, K. Motoyama, T. Tonegawa, N. Ito, K. Arita, Y. Tsuchiya, T. Wake, A. Kubo, K. Sugai, N. Oda, H. Miyamoto, and S. Saito, Proc. IEDM, 265(2000).
2. K. Motoyama, J. Faguet, J. Katsuki, G. Chung, T. Tonegawa and H. Miyamoto, Proc. IITC. 268(2002).
3. W.S. Song, C.S. Lee, K.C. Park, B.S. Suh, J.W. Kim, S.Y. Kim, Y.J. Wee, S.M. Choi, H.-K. Kang, S.U. Kim, K.P. Suh, VLSI Technology Digest of Technical Papers 2002 Symposium, 222(2002).