A selective compressed memory system by on-line data decompressing

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 224-227

  Lee, Jang Soo ^a   Hong, Won Kee ^a   Kim, Shin Dug ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE MEMORY ACCESS TIME; CACHE ARCHITECTURE; COMPRESSION EFFICIENCY; CONVENTIONAL MEMORY; EFFICIENT MANAGEMENTS; MEMORY SYSTEMS; SELECTIVE COMPRESSION; TRACE DRIVEN SIMULATION;

COST REDUCTION; INFORMATION SCIENCE;

CACHE MEMORY;

EID: 84888994889     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794470     Document Type: Conference Paper

References (10)

1. Y.Yoshida, B.Song, H.Okuhata, T.Onoye, and I.Shirakawa. An object code compression approach to embedded-processors. Proc. of the International Symposium on Low Power Electronics and Design, 265-268, 1997.
2. C.Lefurgy, P.Bird, I.Chen, and T.Mudge. Improving code density using compression techniques. Proc. of the 30th Annual International Symposium on Microarchitecture, 194-203, 1997.
3. F.Douglis. The compression cache: Using on-line compression to extend physical memory. Proc. of the Winter USENIX Conference, 519-529, January 1993.
4. M.Kjelso,M.Gooch, and S.Jones. Performance evaluation of computer architectures with main memory data compression. Journal of Systems Architecture, 45: 571-590, 1999.
5. D.Citron and L.Rudolph. Creating a wide bus using caching techniques. Proc. of the first International Symposium on High-Performance Computer Architecture, 90-99, January 1995.
6. M.Farrens and A.Park. Dynamic base register caching: A technique for reducing address bus width. Proc. of the 18th Annual International Symposium on Computer Architecture, 128-137, May 1991.
7. E.A.Kusse and A.J.Isles. On the fly cache compression and decompression. http://infopad.eecs.berkeley.edu/-ekusse/, CS 252 Project, UC Berkeley, 1996.
8. M.Kjelso, M.Gooch, and S.Jones. Design and performance of a main memory hardware data compressor. IEEE Computer Society Press, Prague, Czech Republic, 422-430, September 1996.
9. M.Kjelso, M.Gooch, and S.Jones. Empirical study of memory-data: Characteristic and compressibility. Proc. IEE Computers and Digital Techniques, 145(1): 63-67, January 1998.
10. S.J.E.Wilton and N.P.Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuit, 23(1): 677-688, May 1996.