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Volumn 1998-December, Issue , 1998, Pages 282-285

A low-voltage current-controlled oscillator with low supply dependency

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 84888058139     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.1998.825619     Document Type: Conference Paper
Times cited : (4)

References (8)
  • 2
    • 0030291248 scopus 로고    scopus 로고
    • A 320MHz I.5mW@1.35v CMOS PLL for microprocessor clock eneration
    • Nov
    • V. V. Kaenel, D. Aebischer, C. Piguet, & E. Dijkstra, "A 320MHz I.5mW@1.35v CMOS PLL for microprocessor clock eneration", IEEE J. Solid-State Circuits, vol. 31, no. 11, Nov.1996, pp. 1715-1722.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.11 , pp. 1715-1722
    • Kaenel, V.V.1    Aebischer, D.2    Piguet, C.3    Dijkstra4
  • 3
    • 0031119297 scopus 로고    scopus 로고
    • A lovjitter 0.3-165MHz PLL frequency synthesizer for 3v/5v operation
    • Apr
    • H. C. Yang, L. K. Lee, & R. S. Co, "A lovjitter 0.3-165MHz PLL frequency synthesizer for 3v/5v operation", iEEE 3. Solid-State Circuits, vol;32, no. 4, Apr.1997, pp. 582-586.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.4 , pp. 582-586
    • Yang, H.C.1    Lee, L.K.2    Co, R.S.3
  • 4
    • 0029289215 scopus 로고
    • An all-digital PLL with 50cycle lock time suitable for high-performance microprocessors
    • Apr
    • J. Dunning, G. Garcia, J. Lundberg, & E. Nuckolls, "An all-digital PLL with 50cycle lock time suitable for high-performance microprocessors", IEEE 3. Solid-State Circuits, vol. 30, no. 4, Apr.1995, pp. 412-422.
    • (1995) IEEE 3. Solid-State Circuits , vol.30 , Issue.4 , pp. 412-422
    • Dunning, J.1    Garcia, G.2    Lundberg, J.3    Nuckolls, E.4
  • 6
    • 0030290680 scopus 로고    scopus 로고
    • Low-jitter process-independent DLL & PLL based on self-biased techniques
    • Nov
    • G. Maneatis, "Low-jitter process-independent DLL & PLL based on self-biased techniques", IEEE J. Solid-State Circuits, vol. 31, no. 11, Nov.1996, pp. 1723-1732.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.11 , pp. 1723-1732
    • Maneatis, G.1
  • 7
    • 0031143856 scopus 로고    scopus 로고
    • A 960Mb/s/pin interface for skew-Tolerant bus using low jitter PLL
    • May
    • S. Kim, K. Lee, Y. Moon, 0-K. Jeong, Y. Choi, & H. K. Lim, "A 960Mb/s/pin interface for skew-Tolerant bus using low jitter PLL", IEEE J. Solid-State Circuits, vol. 32, no. 5, May1997, pp. 691-699.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.5 , pp. 691-699
    • Kim, S.1    Lee, K.2    Moon, Y.3    Jeong, O.-K.4    Choi, Y.5    Lim, H.K.6
  • 8
    • 0029244247 scopus 로고
    • Design of high-speed, low-power frequency dividers and PLLs in deep submicron CMOS
    • Feb
    • B. Razavi, K. F. Lee, & R. H. Yan, "Design of high-speed, low-power frequency dividers and PLLs in deep submicron CMOS", IEEE J. Solid-State Circuits, vol. 30, no. 2, Feb.1995, pp. 101-109.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.2 , pp. 101-109
    • Razavi, B.1    Lee, K.F.2    Yan, R.H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.