Event-driven verification of switch-level correctness concerns

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 1998-March, Issue , 1998, Pages 213-223

  Negulescu, Radu ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEMS ANALYSIS;

CIRCUIT SPECIFICATIONS; EVENT-DRIVEN; MOS CIRCUITS; SELF-TIMED; SIGNAL LEVEL; SIGNAL TRANSITION;

DELAY CIRCUITS;

EID: 84885231073     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.1998.657553     Document Type: Conference Paper

References (15)

1. [BRB90] K.S. Brace, R.L. Rudell, and R.E. Bryant. Efficient Implementation of a BDD Package. In Proceedings of the 27th ACM/IEEE Design Automation Conference, June 1990.
2. [Br87] R.E. Bryant. Boolean Analysis of MOS Circuits. In IEEE Transactions on Computer-Aided Design, 4: 634-649, July 1987.
3. [BS95] J.A. Brzozowski, C.J-H. Seger. Asynchronous Circuits. Springer-Verlag, 1995.
4. [Di89] D.L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. MIT Press, 1989.
5. [KS95] T. Kam, P.A. Subrahmanyam. Comparing Layouts with HDL Models: A Formal Verification Technique. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 4: 503-509, April 1995.
6. [KSLP95] A. Kuehlmann, A. Srinivasan, D.P. LaPotin. Verity A formal verification program for custom CMOS circuits. In IBM Journal of Research and Development, 1/2: 149-165, March 1995.
7. [La92] L. Lavagno. Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits. PhD thesis, University of California at Berkeley, 1992.
8. [Ma90] A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C.A.R. Hoare, ed., Developments in Concurrency and Communication, UT Year of Programming Series, pp. 1-64, Addison-Wesley, 1990.
9. [Ne95] R. Negulescu. Process spaces. Technical Report CS-95-48, Department of Computer Science, University of Waterloo, December 1995. http://maveric.uwaterloo.ca/radu/ps.html
10. [Ne97] R. Negulescu. A technique for finding and verifying speed-dependences in digital circuits. In Proceedings of the 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'97), December 1997 (to appear). A technical report is available from: Http://maveric.uwaterloo.ca/radu/ps.html
11. [NP98] R. Negulescu, A.M.G. Peeters. Verification of speed-dependences in single-rail handshake circuits. In Proceedings of the Fourth International Symposium for Advanced Research in Asynchronous Circuits and Systems, San Diego, California, USA, March 1998.
12. [NS95] L.S. Nielsen, J. Staunstrup. Design and verification of a self-timed RAM. In Proceedings of the IFIP International Conference on Very Large Scale Integration 1995, Chiba, Japan, 1995.
13. [St97] J. Staunstrup. Personal communication. 1997.
14. [Ve94] T. Verhoeff. A Theory of Delay-Insensitive Systems. PhD Thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, 1994.
15. [ZH92] C. Zhou and C.A.R. Hoare. A Model for Synchronous Switching Circuits and its Theory of Correctness. In Formal Methods in System Design, 1: 7-28, 1992.