A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2013, Pages

  Chiu, Chao Chang ^a   Huang, Po Hsien ^a   Lin, Moris ^a   Chen, Ke Horng ^a   Lin, Ying Hsi ^b   Tsai, Tsung Yen ^b   Huang, Chen Chih ^b   Lee, Chao Cheng ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

40NM CMOS; INPUT VOLTAGES; LOW DROPOUT REGULATOR; MAXIMUM LOAD; OUTPUT VOLTAGES; POWER SUPPLY REJECTION; SWITCHING NOISE SUPPRESSION;

CMOS INTEGRATED CIRCUITS; LOCKS (FASTENERS); VLSI CIRCUITS; VOLTAGE REGULATORS;

ELECTRIC CURRENT REGULATORS;

EID: 84883782007     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Hirairi, et al., ISSCC Dig. Tech. Papers, pp.486-488, 2012
2. Y.-H. Lee, et al., IEEE J. Solid-State Circuits, Apr. 2013.
3. P. Hazucha, et al., IEEE J. Solid-State Circuits, pp.66-73, 2007
4. Y. Okuma, et al., IEEE Custom Integrated Circuits Conf., pp. 323-326, 2010.
5. Y.-H. Lam, et al., ISSCC Dig. Tech. Papers, pp. 442-443, 2008.