Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013

Volumn , Issue , 2013, Pages 137-142

  Delvaux, Jeroen ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHALLENGE-RESPONSE PAIR; CMOS DEVICES; COMBINED ATTACKS; HARDWARE SECURITY; INFORMATION LEAKAGE; ML ALGORITHMS; MODEL ACCURACY; PHYSICALLY UNCLONABLE FUNCTIONS;

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS;

HARDWARE;

EID: 84883671628     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HST.2013.6581579     Document Type: Conference Paper

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