Development of 3D through silicon stack (TSS) assembly for wide IO memory to logic devices integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2013, Pages 77-80

  Kim, Dong Wook ^a   Vidhya, Ramachandran ^a   Henderson, Brian ^a   Ray, Urmi ^a   Gu, Sam ^a   Zhao, Wei ^a   Radojcic, Riko ^a   Nowak, Matt ^a   Lee, Changmin ^b   Paek, Jongsik ^b   Lee, Kiwook ^b   Huemoeller, Ron ^b  

^a QUALCOMM INC   (United States)

^b AMKOR TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS DEMAND; DEVICE ASSEMBLIES; DEVICES INTEGRATION; ENVIRONMENTAL RELIABILITY; LOWER-POWER CONSUMPTION; MANUFACTURING PROCESS; MOBILE APPLICATIONS; SMALL FORM FACTORS;

APPROXIMATION THEORY; LOGIC DEVICES; MOBILE DEVICES; SILICON; SUPPLY CHAINS;

THREE DIMENSIONAL;

EID: 84883378250     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575553     Document Type: Conference Paper

References (3)

1. S.Q. Gu et al, "Stackable Memory of 3D Chip Integration for Mobile Applications" IEDM Tech. Dig., 2008
2. J. West, et al, "Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect," Symposium on VLSI Technology, art. no. 6242481, pp. 101-102, 2012
3. U.H. Kang et al, "8Gb 3D DDR DRAM using TSV technology," IEEE Journal of Solid State Circuits, vol 45, no. 1, pp. 111-119, Jan. 2010