Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for wide-IO logic-memory interconnect

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 101-102

  West, J ^a   Choi, Y S ^a   Vartuli, C ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

28nm CMOS; context dependent stress; Cu pumping; NBD; proximity effects; TSV; TSV induced strain

Indexed keywords

28NM CMOS; CONTEXT DEPENDENT; NBD; PROXIMITY EFFECTS; TSV;

CMOS INTEGRATED CIRCUITS;

SILICON WAFERS;

EID: 84866557620     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242481     Document Type: Conference Paper

References (9)

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4. C. Huyghebaert, et al, "Enabling 10μm pitch hybrid Cu-Cu IC stacking with TSVs," ECTC pp. 1083-1087, 2010.
5. J. West, USPTO patent pending.
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9. A. Mercha, et al, "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance," IEDM p. 2.2.4, 2010.