Hardware and software implementations of prim's algorithm for efficient minimum spanning tree computation

IFIP Advances in Information and Communication Technology

Volumn 403, Issue , 2013, Pages 151-158

  Mariano, Artur ^a   Lee, Dongwook ^b   Gerstlauer, Andreas ^b   Chiou, Derek ^b  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^b The University of Texas at Austin   (United States)

Author keywords

FPGA; Hardware acceleration; MST; Prim's algorithm

Indexed keywords

HARDWARE ACCELERATION; HARDWARE AND SOFTWARE IMPLEMENTATIONS; MINIMUM SPANNING TREE PROBLEM; MINIMUM SPANNING TREES; MST; NETWORKING APPLICATIONS; OPTIMIZED IMPLEMENTATION; PRIM'S ALGORITHM;

ALGORITHMS; CLOCKS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; OPTIMIZATION; PROGRAM PROCESSORS; WIRELESS AD HOC NETWORKS;

COMPUTATIONAL EFFICIENCY;

EID: 84883045032     PISSN: 18684238     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-38853-8_14     Document Type: Conference Paper

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