Crosstalk noise model for shielded interconnects in VLSI-based circuits

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 243-244

  Zhang, Junmou ^a   Friedman, E G ^a  

^a University of Rochester   (United States)

Author keywords

Capacitance; Circuit noise; CMOS technology; Coupling circuits; Crosstalk; Delay effects; Design methodology; Integrated circuit interconnections; Semiconductor device modeling; Uncertainty

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; CROSSTALK; DELAY CIRCUITS; MICROSTRIP LINES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; UNCERTAINTY ANALYSIS; VLSI CIRCUITS;

CIRCUIT NOISE; CMOS TECHNOLOGY; DELAY EFFECTS; DESIGN METHODOLOGY; INTEGRATED CIRCUIT INTERCONNECTIONS; UNCERTAINTY;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84881654069     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241502     Document Type: Conference Paper

References (1)

1. A. Vittal, L. H. Chen, S. M. Marek, K.-P. Wang, and X. Yang, "Crosstalk in VLSI Interconnections," IEEE Transactions on Computer-Aided Desgin of Integrated Circuits and Systems, Vol. 18, No. 12, pp. 1817-1824, December 1999.