Architectures and issues for gigasample/second ADCs

Analog Circuit Design - High-Speed A-D Converters, Automotive Electronics and Ultra-Low Power Wireless, AACD 2006

Volumn , Issue , 2006, Pages 17-32

  Poulton, Ken ^a   Neff, Robert ^a   Setterberg, Brian ^a   Wuppermann, Bernd ^a   Kopley, Tom ^a  

^a AGILENT LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TECHNOLOGY; DATA STORAGE; FOLDING AND INTERPOLATING; SUCCESSIVE APPROXIMATIONS; TIME-INTERLEAVED; TIME-INTERLEAVING;

ANALOG CIRCUITS;

ARCHITECTURE;

EID: 84881360191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/1-4020-5186-7_2     Document Type: Conference Paper

References (13)

1. MAX108 Datasheet, Maxim Integrated Products.
2. Ken Poulton, Knud L. Knudsen, John Kerley, James Kang, Jon Tani, Eldon Cornish and Michael VanGrouw, "An 8-GSa/s 8-bit ADC System", IEEE VLSI Symposium on Circuits, 1997.
3. Ken Poulton, Knud L. Knudsen, John J. Corcoran, Keh-Chung Wang, Randy Nubling, Richard Pierson, Mau-Chung F. Chang, Peter Asbeck and R.T. Huang, "A 6-bit, 4 GSa/s GaAs HBT ADC", IEEE Journal of Solid State Circuits, Oct 1995.
4. Ken Poulton, John J. Corcoran, Thomas Hornak, "A 1 GHz 6-bit ADC System", IEEE Journal of Solid State Circuits, Dec 1987.
5. J. Corcoran, "High Speed Sample and Hold and Analog-to-Digital Converter Circuits", AACD 1992, published in Johan H. Huijsing, Rudy J. van de Plassche, Willy M.C. Sansen "Analog Circuit Design", Kluwer Academic Publishers, December 1992, ISBN 0-7923-9288-4.
6. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andy Burstein, Mehrdad Heshami "A 4-GSample/s 8b ADC in 0.35-um CMOS", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 166-167, Feb 2002.
7. Ken Poulton, Robert Neff, Brian Setterberg, Bernd Wuppermann, Tom Kopley, Robert Jewett, Jorge Pernillo, Charles Tan, Allen Montijo, "A 20-GSample/s 8b ADC with a 1-MByte Memory in 0.18-um CMOS", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 318-319, Feb 2003.
8. Van der Plas, Geert; Decoutere, Stefaan; Donnay, Stéphane, "A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 566-567, Feb 2006.
9. Figueiredo, Pedro; Cardoso, Paulo; Lopes, Ana; Fachada, Carlos; Hamanishi, Naoyuki; Tanabe, Ken; Vital, Joao, "A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 568-569, Feb 2006.
10. Gupta, Sandeep; Choi, Michael; Inerfield, Michael; Wang, Jingbo, "A 1GS/s 11b Time-Interleaved ADC in 0.13?m CMOS", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 576-577, Feb 2006.
11. Chen, Shuo-Wei; Brodersen, Robert, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13um CMOS", IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 574-575, Feb 2006.
12. P. Schvan, D. Pollex, S-C. Wang, C. Falt, N. Ben-Hamida, "A 22GS/s 5b ADC in 130nm SiGe BiCMOS", IEEE International Solid State Circuits Conference Digest of Technical Papers, Feb 2006.
13. Data courtesy of Boris Murmann.