Discrete event system approach for delay fault analysis in digital circuits

Proceedings of the American Control Conference

Volumn 1, Issue , 1998, Pages 239-243

  Westerman, Glenn ^a   Kumar, Ratnesh ^b   Stroud, Charles ^c   Heath, J Robert ^c  

^a LEXMARK INTERNATIONAL INC   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

^c UNIVERSITY OF KENTUCKY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP DESIGN; CIRCUIT PATH DELAYS; DELAY FAULT ANALYSIS; DELAY FAULT TEST; DELAY FAULTS; FORMAL ANALYSIS; MODELING TECHNIQUE; TESTABILITY EVALUATION;

DYNAMICAL SYSTEMS;

DISCRETE EVENT SIMULATION;

EID: 84881331710     PISSN: 07431619     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACC.1998.694667     Document Type: Conference Paper

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