Exploring processor parallelism: Estimation methods and optimization strategies

Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013

Volumn , Issue , 2013, Pages 18-23

  Jordans, Roel ^a   Corvino, Rosilde ^a   Jozwiak, Lech ^a   Corporaal, Henk ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; ESTIMATION; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS;

APPLICATION SPECIFIC; ESTIMATION METHODS; INTERNAL MEMORY; OPTIMIZATION STRATEGY; PARETO FRONT; PROCESSING SPEED; SILICON AREA; WIDTH ESTIMATIONS;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84881324106     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2013.6549782     Document Type: Conference Paper

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