180nm FRAM reliability demonstration with ten years data retention at 125°C

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2013, Pages

  Rodriguez, J ^a   Rodriguez Latorre, J ^a   Zhou, C ^a   Venugopal, A ^a   Acosta, A ^a   Ball, M ^a   Ndai, P ^a   Madan, S ^a   Mcadams, H ^a   Udayakumar, K R ^a   Summerfelt, S ^a   San, T ^a   Moise, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

180nm analog CMOS; data cycling endurance; data retention; ferroelectric memory; non volatile memory

Indexed keywords

ANALOG CMOS; CYCLING ENDURANCE; DATA RETENTION; FERROELECTRIC MEMORY; NON-VOLATILE MEMORY;

ERROR CORRECTION; LEAD;

DATA STORAGE EQUIPMENT;

EID: 84880967220     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2013.6532102     Document Type: Conference Paper

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5. IPC/JEDEC J-STD-020D.1 (Joint Industry Standard) March, 2008.
6. J. Rodriguez, et al, 2010 IEEE IRPS Proceedings, p. 600.
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