Efficient analysis of pipeline models for WCET computation

OpenAccess Series in Informatics

Volumn 1, Issue , 2007, Pages 37-40

  Wilhelm, Stephan ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION TIME; EFFICIENT ANALYSIS; HARDWARE MODELS; MEMORY CONSUMPTION; PIPELINE MODELS; PROCESSOR PIPELINES; TIMING ANOMALIES; WORST-CASE EXECUTION TIME;

BINARY DECISION DIAGRAMS; STATIC ANALYSIS;

HARDWARE;

EID: 84880085343     PISSN: 21906807     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. http://www.absint.com/aiT/.
2. http://www.avacs.org.
3. A. Aziz, S. Tasiran, and R.K. Brayton. BDD Variable Ordering for Interacting Finite State Machines. In 31st ACM/IEEE Design Automation Conference (DAC), San Diego, CA, 1994.
4. R. Bryant. Graph based algorithms for boolean function manipulation. In IEEE Transactions on Computers, 1986.
5. 20 states and beyond. IEEE Comp. Soc. Press, 1990.
6. S.-T. Cheng. Compiling Verilog into Automata, 1994.
7. C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University, 1997.
8. C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm. Reliable and precise WCET determination for a real-life processor. In Proceedings of EMSOFT 2001, LNCS 2211, 2001.
9. T. Lundquist and P. Stenström. Timing Anomalies in Dynamically Scheduled Microprocessors. In Proceedings of the 20th IEEE Real-Time Systems Symposium, 1999.
10. R. Ranjan, A. Aziz, R. Brayton, B. Plessier, and C. Pixley. Efficient BDD algorithms for FSM synthesis and verification, 1995.
11. The VIS Group. VIS user's manual.
12. H. Theiling. ILP-based Interprocedural Path Analysis. In Proceedings of theWorkshop on Embedded Software, Grenoble, France, 2002.
13. S. Thesing. Safe and Precise WCET Determination by Abstract Interpretation of Pipeline Models. PhD thesis, Saarland University, 2004.