Low power radiation tolerant VLSI for advanced spacecraft

IEEE Aerospace Conference Proceedings

Volumn 5, Issue , 2002, Pages 2401-2406

  Benz, Harry F ^a   Gambles, Jody W ^b   Whitaker, Sterling R ^b   Hass, Kenneth J ^b   Maki, Gary K ^b   Yeh, Pen Shu ^c  

^a NASA LANGLEY RESEARCH CENTER   (United States)

^b UNIVERSITY OF NEW MEXICO   (United States)

^c NASA GODDARD SPACE FLIGHT CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED ELECTRONICS; ORDERS OF MAGNITUDE; RADIATION TOLERANCES; RADIATION TOLERANT; SINGLE EVENT LATCH-UP; SINGLE EVENT UPSETS; TOTAL IONIZING DOSE; ULTRA-LOW-POWER CMOS;

CMOS INTEGRATED CIRCUITS; IONIZING RADIATION;

SPACECRAFT;

EID: 84879334710     PISSN: 1095323X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AERO.2002.1035413     Document Type: Conference Paper

References (11)

1. James B. Burr and Allen M. Peterson, "Ultra Low Power CMOS Technology", NASA Symposium on VLSI Design, pp. 4.2.1-4.2.13, 1991.
2. H.F. Reefs and A.R. Best, "Concatenated Coding on a Spacecraft-to-ground Telemetry Channel Performance", Proc. ICC-8I, 1981.
3. K. J. Hass and H. C. Shaw, "Cryogenic Operation of Ultra Low Power CMOS", 9fc NASA Symposium on VLSI Design, pp. 3.4.1-3.4.7, November 8-9, 2000.
4. J.W. Gambles and G. K. Maki, "Rad-Tolerant Flight VLSI From Commercial Foundries", 39'h Midwest Symposium on Circuits and Systems, pp. 1227-1230, August 1996.
5. S. R. Whitaker, J. W. Gambles, D. Wiseman, and G. K. Maki, "Flight Solid State Recorder Codec", 1995 Government Microcircuit Applications Conference, March 1995.
6. S. Whitaker, J. Canaris and K, Liu, "SEU Hardened Memory Cells for CCSDS Reed Solomon Encoder", IEEE Transactions on Nuclear Science, pp. 1471-1477, December 1991.
7. M. Liu and S. Whitaker, "Low Power SEU Immune CMOS Memory Circuits", IEEE Transactions on Nuclear Science, pp. 1679-1684, December 1992.
8. J. W. Gambles, "A Path Toward Low Cost Rad-Tolerant Digital CMOS", 6'" NASA Symposium on VLSI Design, pp. 1.2.1-1.2.9, March 1997.
9. K. J. Hass, J. Venbrux and P. Bhatia, "Logic Design Considerations for 0.5-Volt CMOS", 2001 Conference on Advanced Research in VLSI, March 14-16,2001.
10. J. Venbrux, G. Zweigle, J. W. Gambles, D. Wiseman, W. Miller and P. Yeh, "An Adaptive Lossless Data Compression Algorithm and VLSI Implementation", 5,h NASA Symposium on VLSI Design, pp. 1.2.1-1.2.16, November 1993.
11. M. A. Xapsos, G. P. Summers, andE.M. Jackson, "Enhanced Ionizing Dose Tolerance Fabricated for Ultra-Low Power Applications", IEEE Transactions on Nuclear Science, December 1999.