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Volumn 1685 LNCS, Issue , 1999, Pages 950-960

A parallel accelerator architecture for multimedia video compression

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE COMPRESSION; SYSTOLIC ARRAYS;

EID: 84878662420     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48311-x_133     Document Type: Conference Paper
Times cited : (8)

References (10)
  • 2
    • 0029291183 scopus 로고
    • New systolic array implementation of the 2-D discrete cosine transform and its inverse
    • Chang, Y.-T., Wang, C.-L.: New Systolic Array Implementation of the 2-D Discrete Cosine Transform and Its Inverse, IEEE Trans. Circ. Syst. Vid. Tech. 5 (2) (1995) 150-157
    • (1995) IEEE Trans. Circ. Syst. Vid. Tech. , vol.5 , Issue.2 , pp. 150-157
    • Chang, Y.-T.1    Wang, C.-L.2
  • 3
    • 0031257902 scopus 로고    scopus 로고
    • A comparison of block-matching algorithms mapped to systolic-array implementation
    • PII S1051821597058849
    • Cheng, S.-C., Hang, H.-M.: A Comparison of Block-Matching Algorithms Mapped to Systolic-Array Implementation, IEEE Trans. Circ. Syst. Video Tech. 7 (5) (1997) 741-757 (Pubitemid 127765237)
    • (1997) IEEE Transactions on Circuits and Systems for Video Technology , vol.7 , Issue.5 , pp. 741-757
    • Cheng, S.-C.1    Hang, H.-M.2
  • 4
    • 0023998903 scopus 로고
    • Instruction systolic array and its relation to other models of parallel computers
    • DOI 10.1016/0167-8191(88)90095-6
    • Kunde, M., et al.: The Instruction Systolic Array and its Relation to Other Models of Parallel Computers, Parallel Computing 7 (1988) 25-39 (Pubitemid 18608306)
    • (1988) Parallel Computing , vol.7 , Issue.1 , pp. 25-39
    • Kunde, M.1    Lang Hans, W.2    Schimmler, M.3    Schmeck, H.4    Schroeder, H.5
  • 5
    • 0022686541 scopus 로고
    • The instruction systolic array, a parallel architecture for VLSI
    • Lang, H.-W.: The Instruction Systolic Array, a parallel architecture for VLSI, Integration, the VLSI Journal 4 (1986) 65-74
    • (1986) Integration, the VLSI Journal , vol.4 , pp. 65-74
    • Lang, H.-W.1
  • 6
    • 84966490118 scopus 로고
    • The instruction systolic array - Implementation of a low-cost parallel architecture as add-on board for personal computers
    • LNCS 797, Springer Verlag
    • Lang, H.-W., Maaß, R., Schimmler, M.: The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers, Proc. HPCN 94, LNCS 797, Springer Verlag (1994) 487-488.
    • (1994) Proc. HPCN 94 , pp. 487-488
    • Lang, H.-W.1    Maaß, R.2    Schimmler, M.3
  • 8
    • 0029748380 scopus 로고    scopus 로고
    • The instruction systolic array in image processing applications
    • SPIE 2784
    • Schimmler, M., Lang, H.-W.: The Instruction Systolic Array in Image Processing Applications, Proc. Europto 96, SPIE 2784 (1996) 136-144
    • (1996) Proc. Europto 96 , pp. 136-144
    • Schimmler, M.1    Lang, H.-W.2
  • 9
    • 84882661285 scopus 로고    scopus 로고
    • Long Operarid Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography
    • Euro-Par'98 Parallel Processing
    • Schmidt, B., Schimmler, M., Schröder, H.: Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application to RSA cryptography, Proc. Euro-Par'98, LNCS 1470, Springer Verlag (1998) 916-922 (Pubitemid 128125166)
    • (1998) Lecture Notes in Computer Science , Issue.1470 , pp. 916-922
    • Schmidt, B.1    Schimmler, M.2    Schroeder, H.3
  • 10
    • 1642300326 scopus 로고    scopus 로고
    • The instruction systolic array in tomographic image reconstruction applications
    • Springer Verlag
    • Schmidt, B., Schimmler, M., Schröder, H.: The Instruction Systolic Array in Tomographic Image Reconstruction Applications, Proc. PART'98, Springer Verlag (1998) 343-354
    • (1998) Proc. PART'98 , pp. 343-354
    • Schmidt, B.1    Schimmler, M.2    Schröder, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.