Tall FIN formation for FINFET devices of 20nm and beyond using multi-cycles of passivation and etch processes

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 8685, Issue , 2013, Pages

  Choi, Dae Han ^a   Yang, Dae Geun ^a   Khanna, Puneet ^a   Maeng, Chang ^a   Hu, Owen ^a   Shen, Hongliang ^a   Wei, Andy ^a   Kim, Sung ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Double patterning; Etch; Fin formation; FINFET; Passivation; Reactive ion etching; Tall fins; Tri gate

Indexed keywords

DOUBLE PATTERNING; ETCH; FIN FORMATION; FINFET; TALL FINS; TRIGATE;

FIELD EFFECT TRANSISTORS; FORCED CONVECTION; HYDROPHILICITY; LOADING; PASSIVATION; REACTIVE ION ETCHING; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON; SILICON WAFERS; SURFACE TENSION;

FINS (HEAT EXCHANGE);

EID: 84878460485     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.2010685     Document Type: Conference Paper

References (5)

1. G. Moore, "Cramming more components onto integrated circuits", Electronic Magazine 38 (8), 4, (1965).
2. st century", Intel Tech. Journal Q3, 1-19 (1998).
3. V. Subramanian, "Multiple gate field-effect transistors for future CMOS technologies", IETE technical review 27, 446-454 (2010).
4. X. Huang, "Sub-50nm P-channel FinFET", IEEE transactions on Electron Devices 48 (5), 880-886, (2001).
5. G. Spierings, "Wet Chemical Etching of Silicate Glasses in Hydrofluoric Acid Based Solutions", Journal of Materials Science 28, 6261-6273 (1993).