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Volumn 2003-January, Issue , 2003, Pages 292-297

Low-power floating-point encoding for signal processing applications

Author keywords

Arithmetic; Convolutional codes; Encoding; Fading; Gaussian noise; Modems; Multimedia systems; Power system modeling; Signal processing; Viterbi algorithm

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONVOLUTIONAL CODES; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); GAUSSIAN NOISE (ELECTRONIC); IMAGE COMMUNICATION SYSTEMS; MICROPROCESSOR CHIPS; MODEMS; MULTIMEDIA SYSTEMS; SYSTEM-ON-CHIP; VITERBI ALGORITHM; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 84878332596     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235685     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 1
    • 0003589319 scopus 로고
    • ANSI/IEEE Std. 754-1985 New York, The institute of Electrical and Electronics Engineers, Inc., August 12
    • "IEEE Standard for Binary Floating-Point Arithmetic" ANSI/IEEE Std. 754-1985 New York, The institute of Electrical and Electronics Engineers, Inc., August 12,1985.
    • (1985) IEEE Standard for Binary Floating-Point Arithmetic
  • 2
    • 0033718137 scopus 로고    scopus 로고
    • Reducing Power by Optimizing the Necessary Precision/Range of Floating Point Arithmetic
    • June
    • J. Tong, D. Nagle, R. Rutenbar "Reducing Power by Optimizing the Necessary Precision/Range of Floating Point Arithmetic". IEEE Trans. On VLSI Vol.8 June 2000.
    • (2000) IEEE Trans. on VLSI , vol.8
    • Tong, J.1    Nagle, D.2    Rutenbar, R.3
  • 5
    • 0035307754 scopus 로고    scopus 로고
    • Limitation of sum of sinusoids fading channel simulators
    • April
    • M.F. Pop, N.C. Belieu "Limitation of sum of sinusoids fading channel simulators" IEEE Trans. On Communication April 2001 Volume 49 Number 4.
    • (2001) IEEE Trans. on Communication , vol.49 , Issue.4
    • Pop, M.F.1    Belieu, N.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.