Wireability comparison of flip chip substrates as a function of chip design and substrate capability

International Microelectronics and Packaging Society - 1st International Conference and Exhibition on Device Packaging 2005: Everything in Electronics Between the Chip and the System

Volumn , Issue , 2005, Pages 314-322

  Memis, Irving ^a  

^a Endicott Interconnect Technologies   (United States)

Author keywords

Chip; Core; Design; Escape; Flip chip; PTH pitch; Substrate; Wiring

Indexed keywords

CHIP; CORE; ESCAPE; FLIP CHIP; PTH PITCH;

DESIGN; ELECTRIC WIRING; EXHIBITIONS; MICROELECTRONICS; PRODUCT DESIGN; SUBSTRATES;

CHIP SCALE PACKAGES;

EID: 84878241990     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. T. Tsukada, S. Tsuchida, and Y. Mashimoto, "Surface Laminar Circuit and Flip Chip Attach Packaging", Proceedings of 7th International Microelectronics Conference, Yokohama, Japan, pp. 252-258, May 1992.
2. T. Nishio, K. Kazushige, Y. Yamaji, N. Takahashi, K. Masanori, R. Malfatt, "An Approach to Reduce Build Up Layers for Flip Chip - Ball Grid Array (FC-BGA) Substrates", 2003 IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium. Session 204, Paper 3, July 2003.
3. J. Audet, D. O'Connor, M. Grinberg, and J. Libous, "Effect of Organic Package Core Via Pitch Reduction on Power Distribution Performance", Proceedings of 2004 Electronic Components and Technology Conference, pp. 1449-1453, June 2004.