Repeater insertion for two-terminal nets in three-dimensional integrated circuits

Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering

Volumn 20 LNICST, Issue , 2009, Pages 141-150

  Xu, Hu ^a   Pavlidis, Vasilis F ^a   Micheli, Giovanni De ^a  

^a EPFL   (Switzerland)

Author keywords

3 D ICs; On chip interconnect; Repeater insertion; Timing optimization

Indexed keywords

3-D ICS; 3-D INTERCONNECTS; CONVENTIONAL APPROACH; CONVENTIONAL METHODS; ON CHIP INTERCONNECT; REPEATER INSERTION; SIMULATION RESULT; THREE DIMENSIONAL INTEGRATED CIRCUITS; TIMING OPTIMIZATION; WIRE DELAYS;

ALGORITHMS; INTEGRATED CIRCUITS; THREE DIMENSIONAL; WIRE;

TELECOMMUNICATION REPEATERS;

EID: 84877865889     PISSN: 18678211     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-04850-0_21     Document Type: Conference Paper

References (9)

1. Bakoglu, H.B., Meindl, J.D.: Optimal Interconnection Circuits for VLSI. IEEE Transactions on Electron Devices 32(5), 903-909 (1985).
2. Dhar, S., Franklin, M.A.: Optimal Buffer Circuits for Driving Long Uniform Lines. IEEE Journal of Solid-State Circuits 26(1), 32-40 (1991).
3. Adler, V., Friedman, E.G.: Uniform Repeater Insertion in RC Trees. IEEE Transactions on Circuits and Systems I 47(10), 1515-1523 (2000). (Pubitemid 32075229)
4. Alpert, C., Devgan, A.: Wire Segmenting for Improved Buffer Insertion. In: IEEE/ACM Design Automation Conference, pp. 588-593 (1997).
5. Pavlidis, V.F., Friedman, E.G.: Timing-Driven Via Placement Heuristics For Threedimensional ICs. Integration, the VLSI Journal 41(4), 489-508 (2008).
6. He, X., Dong, S., Ma, Y., Hong, X.: Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning. In: IEEE International Symposium on Quality Electronic Design, pp. 740-745 (2009.
7. Elmore, W.C.: The Transient Analysis of Damped Linear Networks with Particular Regard to Wideband Amplifiers. Journal of Applied Physics 19(1), 55-63 (1948).
8. Waltz, R.A., Morales, J.L., Nocedal, J., Orban, D.: An Interior Algorithm For Nonlinear Optimization that Combines Line Search and Trust Region Steps. Mathematical Programming 107(3), 391-408 (2006).
9. ASU Predictive Technology Model, http://www.eas.asu.edu/~pmt/.