An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 464-465

  Janssen, Erwin ^a   Doris, Kostas ^a   Zanikopoulos, Athon ^a   Murroni, Alessandro ^a   Van Der Weide, Gerard ^a   Lin, Yu ^a   Alvado, Ludo ^b   Darthenay, Frederic ^b   Fregeais, Yannick ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b NXP SEMICONDUCTORS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FUTURE GENERATIONS; HIGH SPECTRAL PURITY; INTERLEAVED CONVERTERS; MULTICARRIER SIGNAL; NARROWBAND SIGNAL; PERFORMANCE LIMITATIONS; SATELLITE RECEPTION; SOFTWARE-DEFINED RADIOS;

RADIO COMMUNICATION; SIGNAL TO NOISE RATIO;

SYNTHETIC APERTURE RADAR;

EID: 84876555568     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487816     Document Type: Conference Paper

References (3)

1. K. Doris, et al., "A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist," ISSCC Dig. Tech. Papers, pp. 180-181, Feb. 2011
2. C.-Y. Chen and J. Wu, "A 12b 3GS/s Pipeline ADC with 500mW and 0.4 mm2 in 40nm Digital CMOS," IEEE Symp. VLSI Circuits, pp. 120-121, June 2011
3. D. Stepanovic and B. Nikolic, "A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS," IEEE Symp. VLSI Circuits, pp. 84-85, June 2012