Using hardware transactional memory to correct and simplify and readers-writer lock algorithm

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2013, Pages 261-270

  Dice, Dave ^a   Lev, Yossi ^a   Luchangco, Victor ^a   Moir, Mark ^a   Liu, Yujie ^b  

^a ORACLE CORPORATION   (United States)

^b LEHIGH UNIVERSITY   (United States)

Author keywords

hardware transactional memory; readers writer lock

Indexed keywords

BUG FIXES; HARDWARE TRANSACTIONAL MEMORY; SPACE REQUIREMENTS; SYNCHRONIZATION ALGORITHM;

COMPUTER PROGRAMMING LANGUAGES; HARDWARE; PARALLEL PROGRAMMING; STORAGE ALLOCATION (COMPUTER);

ALGORITHMS;

EID: 84875202200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2442516.2442542     Document Type: Conference Paper

References (13)

1. D. Dice, M. Herlihy, D. Lea, Y. Lev, V. Luchangco, W. Mesard, M. Moir, K. Moore, and D. Nussbaum. Applications of the adaptive transactional memory test platform. Transact 2008 workshop, 2008. URL http://labs.oracle.com/projects/ scalable/pubs/TRANSACT2008-ATMTP-Apps.pdf.
2. D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, ASPLOS '09, 2009.
3. D. Dice, Y. Lev, M. Moir, D. Nussbaum, and M. Olszewski. Early experience with a commercial hardware transactional memory implementation. Technical Report TR-2009-180, Sun Microsystems Laboratories, 2009.
4. D. Dice, Y. Lev, V. J. Marathe, M. Moir, D. Nussbaum, and M. Oleszewski. Simplifying concurrent algorithms by exploiting hardware transactional memory. In Proceedings of the 22nd ACM symposium on Parallelism in algorithms and architectures, SPAA '10, 2010.
5. D. Dice, Y. Lev, Y. Liu, V. Luchangco, and M. Moir. Using hardware transactional memory to correct and simplify a readers-writer lock algorithm, 2013. URL http://labs.oracle.com/projects/scalable/pubs/PPoPP2013-HTM-RWlocks- appendix.pdf.
6. A. Dragojević and T. Harris. STM in the small: trading generality for performance in software transactional memory. In Proceedings of the 7th ACM european conference on Computer Systems, EuroSys '12, pages 1-14, New York, NY, USA, 2012. ACM. ISBN 978-1-4503-1223-3. doi: 10.1145/2168836.2168838. URL http://doi.acm.org/10.1145/2168836.2168838.
7. M. Greenwald and D. Cheriton. The synergy between non-blocking synchronization and operating system structure. In Proceedings of the second USENIX symposium on Operating systems design and implementation, OSDI '96, pages 123-136, New York, NY, USA, 1996. ACM. ISBN 1-880446-82-0. doi: 10.1145/238721.238767. URL http://doi.acm.org/10.1145/238721.238767.
8. O. Krieger, M. Stumm, R. Unrau, and J. Hanna. A fair fast scalable rea,der-writer lock. In Proceedings of the 1993 International Conference on Parallel Processing - Volume 02, ICPP '93, pages 201-204, Washington, DC, USA, 1993. IEEE Computer Society. ISBN 0-8493-8983-6. doi: 10.1109/ICPP.1993.21. URL http://dx.doi.org/10.1109/ICPP.1993.21.
9. Y. Lev, V. Luchangco, and M. Olszewski. Scalable reader-writer locks. In Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures, SPAA '09, pages 101-110, New York, NY, USA, 2009. ACM. ISBN 978-1-60558-606-9. doi: 10.1145/1583991.1584020. URL http://doi.acm.org/10.1145/ 1583991.1584020.
10. J. M. Mellor-Crummey and M. L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst., 9(1):21-65, Feb. 1991. ISSN 0734-2071. doi: 10.1145/103727.103729. URL http://doi.acm.org/10.1145/103727.103729.
11. R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proc. 34th International Symposium on Microarchitecture, pages 294-305, Dec. 2001.
12. I. Sparc International. The sparc architecture manual, version 8, 1991. URL http://www.sparc.org/standards/V8.pdf.
13. M. Tremblay and S. Chaudhry. A third-generation 65nm 16-core 32-thread plus 32-scout-thread CMT SPARC® processor. In IEEE International Solid-State Circuits Conference, Feb. 2008.