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Volumn , Issue , 2012, Pages 846-852

A novel and flexible test stand for medium voltage drives using a hardware-in-loop (HIL) simulator

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX TOPOLOGY; CONTROL STRATEGIES; FIELD TESTING; HARDWARE-IN-LOOP; MEDIUM VOLTAGE DRIVES; OPTIMIZED DESIGNS; SYSTEM ARCHITECTURES; TEST STANDS;

EID: 84874141795     PISSN: None     EISSN: 21913358     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (9)
  • 2
    • 0032687527 scopus 로고    scopus 로고
    • Rail vehicle control system integration testing using digital hardware-in-the-loop simulation
    • May
    • P. Terwiesch, T. Keller, E. Scheiben, "Rail Vehicle Control System Integration Testing Using Digital Hardware-in-the-Loop Simulation", IEEE Trans. On Control Systems Technology, Vol. 7, No. 3, May 1999.
    • (1999) IEEE Trans. on Control Systems Technology , vol.7 , Issue.3
    • Terwiesch, P.1    Keller, T.2    Scheiben, E.3
  • 7
    • 79953194754 scopus 로고    scopus 로고
    • A combined state-space nodal method for the simulation of power system transients
    • April
    • C. Dufour, J. Mahseredjian, J. Belanger, "A Combined State-Space Nodal Method for the Simulation of Power System Transients", IEEE Transactions on Power Delivery, Vol. 26, No. 2, April 2011, pp. 928-935.
    • (2011) IEEE Transactions on Power Delivery , vol.26 , Issue.2 , pp. 928-935
    • Dufour, C.1    Mahseredjian, J.2    Belanger, J.3
  • 8
    • 33646346102 scopus 로고    scopus 로고
    • A versatile cluster-based real-time digital simulator for power engineering research
    • May
    • L.-F. Pak, O. Faruque, X. Nie, V. Dinavahi, "A Versatile Cluster-Based Real-Time Digital Simulator for Power Engineering Research", IEEE Transactions on Power Systems, Vol. 21, No. 2, pp. 455- 465, May 2006.
    • (2006) IEEE Transactions on Power Systems , vol.21 , Issue.2 , pp. 455-465
    • Pak, L.-F.1    Faruque, O.2    Nie, X.3    Dinavahi, V.4
  • 9
    • 44349139605 scopus 로고    scopus 로고
    • FPGA-based ultra-low latency HIL fault testing of a permanent magnet motor drive using RT-LAB-XSG
    • SAGE Publications, February/March
    • C.Dufour, J. Bélanger, V. Lapointe, "FPGA-Based Ultra-Low Latency HIL Fault Testing of a Permanent Magnet Motor Drive using RT-LAB-XSG", Simulation: Transactions of the Society for Modelling and Simulation International, SAGE Publications, Vol.84, Issue 2/3, February/March 2008, pp. 161-172.
    • (2008) Simulation: Transactions of the Society for Modelling and Simulation International , vol.84 , Issue.2-3 , pp. 161-172
    • Dufour, C.1    Bélanger, J.2    Lapointe, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.