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Volumn 84, Issue 2-3, 2008, Pages 161-172

FPGA-based ultra-low latency HIL fault testing of a permanent magnet motor drive using RT-LAB-XSG

Author keywords

FPGA; Hardware In the Loop; PMSM simulation; Real time simulation

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INDUCTION MOTORS; PULSE WIDTH MODULATION; REAL TIME SYSTEMS; SYNCHRONOUS MOTORS;

EID: 44349139605     PISSN: 00375497     EISSN: 17413133     Source Type: Journal    
DOI: 10.1177/0037549708091537     Document Type: Conference Paper
Times cited : (16)

References (8)
  • 6
    • 0242496415 scopus 로고    scopus 로고
    • "Modeling and Simulation of FPGA-based Variable-Speed Drives using Simulnk"
    • F. Ricci, H. Le-Huy, "Modeling and Simulation of FPGA-based Variable-Speed Drives using Simulnk", Mathematics and Computers in Simulation 63 (2003) pp. 183-195
    • (2003) Mathematics and Computers in Simulation , vol.63 , pp. 183-195
    • Ricci, F.1    Le-Huy, H.2
  • 7
    • 53849116459 scopus 로고    scopus 로고
    • "Hardware-In-the-Loop Simulation of Finite-Element Based Motor Drives with RT-LAB and JMAG"
    • Yokohama, Japan, October 23-28
    • S. Abourida, C. Dufour, J. Bélanger, T. Yamada, T. Arasawa, "Hardware-In-the-Loop Simulation of Finite-Element Based Motor Drives with RT-LAB and JMAG", EVS-22 Symposium, Yokohama, Japan, October 23-28, 2006.
    • (2006) EVS-22 Symposium
    • Abourida, S.1    Dufour, C.2    Bélanger, J.3    Yamada, T.4    Arasawa, T.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.