A stochastic neural architecture that exploits dynamically reconfigurable FPGAs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1993, Pages 202-211

  Van Daalen, M ^a   Jeavons, P ^a   Shawe Taylor, J ^a  

^a UNIVERSITY OF LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; NETWORK ARCHITECTURE; REAL TIME CONTROL; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

DIGITAL ARCHITECTURE; DIGITAL CIRCUITRY; FINE GRAINED; NEURAL ARCHITECTURES; REAL-TIME IMPLEMENTATIONS; RECONFIGURABLE; SPECIFIC VALUES; STOCHASTIC COMPUTING;

STOCHASTIC SYSTEMS;

EID: 84873871151     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1993.279462     Document Type: Conference Paper

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