General-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA

IECON Proceedings (Industrial Electronics Conference)

Volumn , Issue , 2012, Pages 3073-3081

  Dufour, Christian ^a   Cense, Sebastien ^a   Ould Bachir, Tarek ^b   Gregoire, Luc Andre ^a   Belanger, Jean ^a  

^a OPAL RT TECHNOLOGIES   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE IN-THE-LOOP SIMULATION; LOW-LATENCY; MOTOR DRIVE;

ELECTRIC DRIVES; ELECTRIC LINES; ELECTRIC NETWORK ANALYSIS; HARDWARE; INDUSTRIAL ELECTRONICS; NETWORKS (CIRCUITS);

RECONFIGURABLE HARDWARE;

EID: 84872893761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2012.6389407     Document Type: Conference Paper

References (11)

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