Evaluating the worst-case performance of flash translation layer

Communications in Computer and Information Science

Volumn 341 CCIS, Issue , 2012, Pages 27-33

  Shin, Ilhoon ^a  

^a Seoul National University of Science and Technology   (South Korea)

Author keywords

flash translation layer; NAND based block devices; worst case performance

Indexed keywords

COMPUTER SCIENCE; COMPUTERS;

BEST WORST-CASE PERFORMANCE; BLOCK DEVICES; COMPUTING DEVICES; DRIVE SIMULATION; FLASH TRANSLATION LAYER; PAGE MAPPINGS; WORST-CASE PERFORMANCE;

NAND CIRCUITS;

EID: 84869752124     PISSN: 18650929     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-35248-5_5     Document Type: Conference Paper

References (5)

1. Ban, A.: Flash file system. United States Patent, No. 5,404,485 (1995).
2. Ban, A.: Flash file system optimized for page-mode flash technologies. United States Patent, No. 5,937,425 (1999)
3. Kim, J., Kim, J.M., Noh, S., Min, S., Cho, Y.: A space-efficient flash translation layer for compactflash systems. IEEE Transactions on Consumer Electronics 48, 366-375 (2002)
4. Lee, S., Park, D., Chung, T., Choi, W., Lee, D., Park, S., Song, H.: A log buffer based flash translation layer using fully associative sector translation. ACM Transactions on Embedded Computing Systems 6(3) (2007)
5. Shin, I.: Light weight sector mapping scheme for NAND-based block devices. IEEE Transactions on Consumer Electronics 56, 651-656 (2010)