FPGA implementation for real-time empirical mode decomposition

IEEE Transactions on Instrumentation and Measurement

Volumn 61, Issue 12, 2012, Pages 3175-3184

  Hong, Ying Yi ^a   Bao, Yu Qing ^b  

^a CHUNG YUAN CHRISTIAN UNIVERSITY   (Taiwan)

^b SOUTHEAST UNIVERSITY   (China)

Author keywords

Field programmable gate arrays (FPGAs); pipeline processing; real time systems; signal analysis

Indexed keywords

COMPUTATIONAL EFFICIENCY; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; HIGH LEVEL LANGUAGES; ITERATIVE METHODS; REAL TIME SYSTEMS; SIGNAL ANALYSIS;

CIRCULAR QUEUE; COMPUTATIONAL PROCESS; DSP CHIP; EMPIRICAL MODE DECOMPOSITION; END EFFECTS; FAST PROCESS; FPGA IMPLEMENTATIONS; HARDWARE ENVIRONMENT; HIGH-LEVEL COMPUTER LANGUAGES; INTRINSIC MODE FUNCTIONS; LOWER ENVELOPES; PIPELINE PROCESSING; PIPELINE STRUCTURE; QUARTUS II; REAL TIME; REAL-TIME APPLICATION; REAL-TIME COMPUTATIONS; SAMPLING RATES;

SIGNAL PROCESSING;

EID: 84869502169     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2012.2211460     Document Type: Article

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