TSV optimization for BEOL interconnection in logic process

2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Volumn , Issue , 2011, Pages

  Kang, Sinwoo ^a   Cho, Sungdong ^a   Yun, Kiyoung ^a   Ji, Sangwook ^a   Bae, Kisoon ^a   Lee, Woonseob ^a   Kim, Eunji ^a   Kim, Jangho ^a   Cho, Jonghoon ^a   Mun, Hyongyol ^a   Park, Yeong L ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH RELIABLE; HIGH TEMPERATURE HEAT TREATMENT; LOGIC PROCESS;

DELAMINATION;

EXTRUSION;

EID: 84866862177     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2012.6262947     Document Type: Conference Paper

References (3)

1. P.C. Andricacos et al., "Damascene copper plating for chip Interconnections," IBM J. Res. Dev. 42 567-74 (1998)
2. J.C. Lin et al., IEDM (2010)
3. R.Patti, 3D-ASP, (2008)