Comparison of advanced PoP package configurations

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1946-1950

  Eslampour, Hamid ^a   Lee, Seongmin ^a   Park, Seongwon ^a   Lee, Taekeun ^a   Yoon, Insang ^a   Kim, Youngchul ^a  

^a STATS ChipPAC Ltd   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D PACKAGING; APPLICATION PROCESSORS; BASE BANDS; MARKET DEMAND; MEMORY MODULES; PACKAGE CONFIGURATIONS; SOLDER BALLS; STACKED PACKAGE; VERTICAL INTEGRATION;

DATA STRUCTURES; DIES; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONICS PACKAGING; FLASH MEMORY; TECHNOLOGY;

PACKAGING;

EID: 77955185868     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490687     Document Type: Conference Paper

References (6)

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2. JEDEC, " High Temperature Package Warpage Measurement Methodology", JESD22-B112, May 2005
3. JESD22-A104D; Temperature Cycling, May 2005
4. J-STD-020D.1; Mositure/Reflow Sensitivity Classification, March 2008
5. JESD22-A110-B; Highly-Accelerated Temperature and Humidity Stress Test. Feb. 1999
6. JESD22-A103C; High Temperature Storage Life test, Nov 2004.