A 10-bit 1-GHz 33-mW CMOS ADC

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 30-31

  Sahoo, Bibhu Datta ^a   Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR MISMATCH; CMOS ADC; CMOS TECHNOLOGY; GAIN ERRORS; PIPELINED ADCS;

VLSI CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 84866627573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243774     Document Type: Conference Paper

References (4)

1. E. Siragusa and I. Galton, "A Digitally Enhanced 1.8-V 15-bit 40-MSamples/s CMOS Pipelined ADC", IEEE JSSC, pp. 2126-2138, Dec. 2004.
2. B. Sahoo and B. Razavi, "A 12-Bit 200-MHz CMOS ADC", IEEE JSSC, pp. 2366-2380, Sept. 2009.
3. A. N. Karanicolas, H. Lee, and K. Bacrania, "A 15-b 1-Msamples/s Digitally Self-Calibrated Pipeline ADC," IEEE JSSC, pp. 2040-2050 , Dec. 1993.
4. Jan Mulder et al, "An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS," ISSCC Dig. Tech. Papers, pp. 184-185, Feb. 2011.