An aVLSI programmable axonal delay circuit with spike timing dependent delay adaptation

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 2413-2416

  Wang, Runchun ^a   Tapson, Jonathan ^a   Hamilton, Tara Julia ^a   Van Schaik, Andre ^a  

^a UNIVERSITY OF WESTERN SYDNEY   (Australia)

Author keywords

analogue VLSI; axonal propagation delay; delay adaptation; spiking neurons

Indexed keywords

ANALOGUE VLSI; DELAY ADAPTATION; PROPAGATION DELAYS; SPIKE TIMING; SPIKING NEURAL NETWORKS; SPIKING NEURON;

NEURAL NETWORKS;

VLSI CIRCUITS;

EID: 84866627549     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2012.6271785     Document Type: Conference Paper

References (4)

1. E. M. Izhikevich,"Polychronization: computation with spikes.," Neural computation, vol. 18, no. 2, pp. 245-82, Feb. 2006.
2. W. Gerstner, R. Kempter, J. L. van Hemmen, and H. Wagner,"A neuronal learning rule for sub-millisecond temporal coding.," Nature, vol. 383, no. 6595, pp. 76-81, Sep. 1996.
3. R. Wang, J. Tapson, T. J. Hamilton, and A. van Schaik,"An analogue VLSI implementation of polychronous spiking neural networks," in The International Conference Series on Intelligent Sensors, Sensor Networks and Information Processing, 2011.
4. D. Python and C. C. Enz,"A micropower class-AB CMOS log-domain filter for DECT applications," IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1067-1075, Jul. 2001.