A class-G dual-supply switched-capacitor power amplifier in 65nm CMOS

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2012, Pages 233-236

  Yoo, Sang Min ^a   Jann, Benjamin ^b   Degani, Ofir ^c   Rudell, Jacques C ^a   Sadhwani, Ram ^b   Walling, Jeffrey S ^d   Allstot, David J ^a  

^a University of Washington   (United States)

^b INTEL CORPORATION   (United States)

^c INTEL CORPORATION   (Israel)

^d RUTGERS UNIVERSITY   (United States)

Author keywords

CMOS integrated circuits; EER; polar transmitters; power amplifiers; power combining circuits; switched capacitor circuits

Indexed keywords

2.4 GHZ-BAND; DIGITAL LOGIC; DIGITAL PREDISTORTION; DIGITAL-TO-ANALOG; EER; IEEE 802.11G; OUTPUT POWER; POLAR TRANSMITTER; POWER COMBINING; RF POWER AMPLIFIERS; SIGNAL ENVELOPE; SWITCHED CAPACITOR; SWITCHED CAPACITOR CIRCUITS;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; POWER AMPLIFIERS; STANDARDS; SWITCHING FUNCTIONS;

CAPACITORS;

EID: 84866607983     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2012.6242271     Document Type: Conference Paper

References (8)

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7. J. S. Walling, et al., "A 28.6 dBm 65 nm class-E PA with envelope restoration by pulse-width and pulse-position modulation," IEEE Int. Solid-State Circuits Conf., 2008, pp. 566-567.
8. B. Serneels, et al., "A 5.5 V SOPA line driver in a standard 1.2 V 0.13 mm CMOS technology," IEEE European Solid-State Circuits Conf., 2005, pp. 303-306.